A semiconductor memory device typically includes an array of memory cells arranged in rows and columns, with each memory cell configured to store one or more bits of data. The memory cells within a given row of the array are coupled to a common wordline, while the memory cells within a given column of the array are coupled to a common bitline. Thus, the array includes a memory cell at each point where a wordline intersects with a bitline.
In a semiconductor memory device of the type described above, data may be written to or read from the memory cells of the array using a memory cycle that is divided into a precharge phase and an active phase, with the precharge phase being used to precharge the bitlines to a precharge voltage, and the active phase being used to read or write one or more memory cells of the array. Reading a given memory cell generally comprises transferring data stored within that cell to its corresponding bitline, and writing a given memory cell generally comprises transferring data into that cell from its corresponding bitline.
The speed of data transfer from the memory cells to the bitlines during a read operation, or from the bitlines to the memory cells during a write operation, is often dependent upon the gain or other characteristics of a memory cell transistor. This is typically the case, for example, in dynamic random access memory (DRAM), Flash memory, and read-only memory (ROM). In many implementations, the cell transistor may be an n-channel transistor, while the associated precharge circuitry comprises one or more p-channel precharge transistors. This can create a problem, in that the relative strengths of the n-channel cell transistors and the p-channel precharge transistors may differ due to process conditions, leading to variations in the durations of the precharge and active phases of the memory cycle. However, the memory device generally must have a memory cycle of predetermined length, usually determined by one or more of the capability of the memory and the application of the memory.
In conventional practice, the predetermined length of the memory cycle is set so as to be long enough to accommodate both the worst case precharge phase duration and the worst case active phase duration, even though the worst case precharge phase duration and the worst case active phase duration typically occur under different process conditions. In the above-noted example involving n-channel cell transistors and p-channel precharge transistors, the worst case or longest precharge phase duration occurs under process conditions yielding relatively weak p-channel transistors, and the worst case or longest active phase duration occurs under process conditions yielding relatively weak n-channel transistors. As a result, the memory cycle length is unduly increased, which can lead to higher power consumption in the memory device. The power supply operating range and manufacturing yield can also be adversely impacted.
It is therefore apparent that a need exists for an improved approach to controlling the respective durations of precharge and active phases of a memory cycle of a memory device in the presence of process variations.